a0~a18 /oe /we /cs d0~7 512k x 8 sram 512k x 8 sram decoder a19 /cs /cs 512k x 8 sram /cs 512k x 8 sram /cs a20 address inputs a0 - a20 a0 - a20 a0 - a20 a0 - a20 a0 - a20 data input/output d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 chip select cs cs cs cs cs write enable we we we we we output enable oe oe oe oe oe no connect nc nc nc nc nc power (+5v) v v v v v cc cc cc cc cc ground gnd gnd gnd gnd gnd package details package details package details package details package details sys82000rkxd - 85/10/12 sys82000rkxd - 85/10/12 sys82000rkxd - 85/10/12 sys82000rkxd - 85/10/12 sys82000rkxd - 85/10/12 block diagram block diagram block diagram block diagram block diagram pin functions pin functions pin functions pin functions pin functions pin definition pin definition pin definition pin definition pin definition description description description description description features features features features features issue 1.4 : april 2001 2m x 8 sram module 2m x 8 sram module 2m x 8 sram module 2m x 8 sram module 2m x 8 sram module ? access times of 85/100/120ns. 36 pin industry standard single-in-line package. 5 volt supply 10% . power dissipation : operating (min cycle) 610 mw (max). standby -l version (cmos) 2.2 mw (max). completely static operation. equal access and cycle times. low voltage v cc data retention. directly ttl compatible. on-board decoding & capacitors. compatible with the sys8512rkx, sys81000rkxb and sys82000rkx modules. the sys82000rkxd is a plastic 16mbit static ram module housed in a standard 36 pin single-in- line package organised as 2m x 8. this offers an extremely high pcb packing density. the module is constructed using four 512kx8 srams in tsopii packages mounted on a fr4 epoxy substrate. access times are 85, 100 and 120ns. the sys82000rkxd is offered in standard and low power versions, with the -l module having a low voltage data retention mode for battery backed applications. plastic 36 pin single-in-line (sip) a20 vcc we d2 d3 d0 a1 a2 a3 a4 gnd d5 a10 a11 a5 a13 a14 a19 cs a15 a16 a12 a18 a6 d1 gnd a0 a7 a8 a9 d7 d4 d6 a17 vcc oe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
sys82000rkxd - 70/85/10/12 issue 1.3 february 2000 2 parameter symbol test condition min typ max unit i/p leakage current address,oe,we i li 0v < v in < v cc -4 - 4 a output leakage current i lo cs = v ih, v i/o = gnd to v cc -4 - 4 a average supply current i cc1 min. cycle, cs = v il ,v il v cc -0.2v, 0.2 v cc -0.2v, 0.2 sys82000rkxd - 70/85/10/12 issue 1.3 february 2000 3 * input pulse levels: 0v to 3.0v * input rise and fall times: 5ns * input and output timing reference levels: 1.5v * output load: see diagram * v cc =5v10% ac test conditions ac test conditions ac test conditions ac test conditions ac test conditions output load output load output load output load output load operation truth table operation truth table operation truth table operation truth table operation truth table 645 100pf i/o pin 1.76v ? parameter symbol test condition min typ (1) max unit v cc for data retention v dr cs > v cc -0.2v data retention current v cc = 3.0v, cs > v cc -0.2v 2.0 - - v i ccdr1 (2) t op = 0c to 40c - - 220 a chip deselect to data retention time t cdr see retention waveform 0 - - ns operation recovery time t r see retention waveform 5 - - ms notes (1) typical figures are measured at 25c. (2) this parameter is guaranteed not tested. low v low v low v low v low v cc cc cc cc cc data retention characteristics - l version only data retention characteristics - l version only data retention characteristics - l version only data retention characteristics - l version only data retention characteristics - l version only cs oe we data pins supply current mode h x x high impedance i sb1 , i sb2 , i sb3 standby l l h data out i cc1 read l h l data in i cc1 write l l l data in i cc1 write l h h high-impedance i sb1 , i sb2 , i sb3 high-z notes : h = v ih : l =v il : x = v ih or v il
sys82000rkxd - 70/85/10/12 issue 1.3 february 2000 4 write cycle write cycle write cycle write cycle write cycle -85 - 10 -12 parameter symbol min max min max min max unit write cycle time t wc 85 - 100 - 120 - ns chip selection to end of write t cw 75-80-100-ns address valid to end of write t aw 75-80-100-ns address setup time t as 0-0-0-ns write pulse width t wp 55 - 60 - 70 - ns write recovery time t wr 3-3-3-ns write to output in high z t whz 030035040ns data to write time overlap t dw 35 - 40 - 45 - ns data hold from write time t dh 0-0-0-ns output active from end of write t ow 5-5-5-ns -85 -10 -12 parameter symbol min max min max min max unit read cycle time t rc 85 - 100 - 120 - ns address access time t aa - 85 - 100 - 120 ns chip select access time t acs - 85 - 100 - 120 ns output enable to output valid t oe -45-50-60ns output hold from address change t oh 10 - 10 - 10 - ns chip selection to output in low z t clz 10 - 10 - 10 - ns output enable to output in low z t olz 5-5-5-ns chip deselection to o/p in high z t chz 030035045ns output disable to output in high z t ohz 030035045ns read cycle read cycle read cycle read cycle read cycle ac operating conditions
sys82000rkxd - 70/85/10/12 issue 1.3 february 2000 5 read cycle timing waveform read cycle timing waveform read cycle timing waveform read cycle timing waveform read cycle timing waveform (1,2) write cycle no.1 timing waveform write cycle no.1 timing waveform write cycle no.1 timing waveform write cycle no.1 timing waveform write cycle no.1 timing waveform (1,4) t wr(7) as(6) t cw t wp(2) t dw dh aw don't care t t t t t wc ohz(3,9) address oe cs we dout din hi g h-z hi g h-z ow t (8) data valid oe t acs t clz (4,5) t ohz (3) t t olz aa oh chz (3,4,5) data valid t t t t rc address cs dout oe don't care. ac read characteristics notes (1) we is high for read cycle. (2) all read cycle timing is referenced from the last valid address to the first transition address. (3) t chz and t ohz are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) at any given temperature and voltage condition, t chz (max) is less than t clz (min) both for a given module and from module to module. (5) these parameters are sampled and not 100% tested.
sys82000rkxd - 70/85/10/12 issue 1.3 february 2000 6 write cycle no.2 timing waveform write cycle no.2 timing waveform write cycle no.2 timing waveform write cycle no.2 timing waveform write cycle no.2 timing waveform (1,5) (1,5) (1,5) (1,5) (1,5) t r t cdr 4.5v 2.2v 4.5v 2.2v 0v data retention mode vcc cs v dr cs > vcc -0.2v data retention waveform data retention waveform data retention waveform data retention waveform data retention waveform ac write characteristics notes (1) all write cycle timing is referenced from the last valid address to the first transition address. (2) all writes occur during the overlap of cs and we low. (3) if oe, cs, and we are in the read mode during this period, the i/o pins are low impedance state. inputs of opposite phase to the output must not be applied because bus contention can occur. (4) dout is the read data of the new address. (5) oe is continuously low. (6) address is valid prior to or coincident with cs and we low, too avoid inadvertant writes. (7) cs or we must be high during address transitions. (8) when cs is low : i/o pins are in the output state. input signals of opposite phase leading to the output should not be applied. (9) defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. t aw t cw wr(7) wc as(6) dw dh oh ow whz(3,9) wp(2) don't t t t t t address cs we dout din t t t t care hi g h-z hi g h-z (4) (8) data valid
sys82000rkxd - 70/85/10/12 issue 1.3 february 2000 7 SYS82000RKXDLI-85 speed 85 = 85 ns 10 = 100 ns 12 = 120 ns temperature range blank = commercial temperature i = industrial temperature power consumption blank = standard part l = low power part package rkxd = p lastic 36 pin single-in-line (sip) organization 82000 = 2m x 8 memory type sys = static ram package information dimensions in mm ordering information plastic 36 pin single-in-line (sip) 15.70 max 97.20 max 3.40 max 0.50 typ. 2.54 typ. 3.50 +/- 0.50 1 1.00 note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for aparticular purpose. our products are subject to a constant process of development. data may be changed without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director.
|
